The invention relates to a system and method for signal transmission, including the transmission of differential signals, and to a signal modulation and a signal demodulation device.
In electric or electronic systems, individual system modules, e.g., different electronic components, different electronic devices arranged on a single component (e.g., different semiconductor devices arranged on a single component), different device subcomponents provided in one and the same device (in particular different components of a semiconductor device), etc. communicate via a transmission medium consisting of one or a plurality of transmission lines, for instance, a bus system.
Bus systems may be used jointly by several, in particular by more than two system modules, and may, for instance, consist of several partial systems, e.g., of a data bus for the transmission of the actual payload, and/or an address bus for the transmission of address data, and/or a control bus for the transmission of control data, etc.
Between the individual system modules (e.g., between individual semiconductor devices (for instance, a DRAM (DRAM=Dynamic Random Access Memory or dynamic read-write memory) and a DRAM controller; a microcontroller or microprocessor and a further device, etc.)), the respective data can always be transmitted in two different ways, namely either by a single line (i.e. in a “single-wired” manner), or e.g., by a line pair (i.e. in a “double-wired” manner).
Both in the case of the single-wired and the double-wired transmission of data the effort is usually made to terminate the line or the lines, respectively, at the respectively receiving module with a (termination) resistor R that is identical to the impedance ZW of the line(s) (“line adaptation”). Thus, the line losses and (undesired) signal reflections can be minimized.
The transmission of data via corresponding line pairs (“two-wired data transmission”) is generally performed by differential or symmetric signals that are output by corresponding interface circuit arrangements provided in the respective system module, e.g., by signals corresponding to the LVDS (Low Voltage Differential Signaling) standard ANSI TIA/EIA-644.
For applying the corresponding differential or symmetric signals to a line pair, two—cooperating—voltage or current sources may be provided in the respective interface circuit arrangement at the module acting as transmission module.
The first voltage source of the interface circuit arrangement may, for instance, be connected between a first line of the line pair and the ground (or a corresponding bias), and the second voltage source may be connected with the second line of the line pair, and—also—with the ground (or a corresponding bias).
If the first voltage source outputs a “high-level signal” (i.e., for instance, a voltage of US1≈2.5 V), the second voltage source—simultaneously—outputs a “low-level” signal (i.e., for instance, a voltage of US2≈0.5 V).
Vice versa, if the first voltage source outputs a “low-level signal” (i.e., for instance, a voltage of US1≈0.5 V), the second voltage source—simultaneously—outputs a “high-level” signal (i.e., for instance, a voltage of US2≈2.5 V).
This way, digital data may be transmitted via the line pair from the transmitting to the receiving module (e.g., voltage intensities of US1=2.5 V and US2=0.5 V correspond, for instance, to a transmitted “1”, and voltage intensities of US1=0.5 V and US2=2.5 V to a transmitted “0” (or vice versa)).
The applying of the above-mentioned voltages results in a corresponding current flow either from the first voltage source (“source A”)—via the line pair—to the second voltage source (“source B”), or vice versa from the second voltage source (“source B”)—via the line pair—to the first voltage source (“source A”), and thus in a corresponding positive or negative voltage drop at the (termination) resistor provided at the receiving module.
By sensing the respective voltage drop occurring at the (termination) resistor it can thus be determined whether a “1” or a “0” was transmitted via the line pair.
As a rule, for the transmission of data (payload, address data, control data) by corresponding differential or symmetric signals—in addition to one or several line pairs that direct the actual data—at least one further line pair is required via which a corresponding (differential) clock signal is transmitted, i.e. corresponding timing data.
By corresponding state changes of the differential clock signal transmitted via the clock line pair, the points in time can be determined at which the voltage drop at the receiving module is to be sensed at the (termination) resistor provided for the data line pair directing the actual data.
For these and other reasons, there is a need for the present invention.